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1 36-00-00-000 ver. 1.3.1 aeroflex microelectronics solutions - hirel features ? supports up to 166 mhz clock rate ? separate instruction and data cache architecture ? high-performance fully pipelined ieee-754 fpu ? enhanced pipeline with 1.2 dmips / mhz performance ? implemented on 130nm cmos technology ? internally configured clock network ? power saving 1.2v core power supply ? 3.3v i/o compatibility ? hardened-by-design flip-flops and memory cells ? reed solomon edac ? multifunctional memory controller ? 10/100 base-t ethernet port for vxworks development ? integrated pci 2. 2 compatible core ? four integrated multi-pr otocol spacewire nodes that support the rmap protocol ? spi interface ? two can 2.0 compliant bus interfaces ? mil-std-1553 bc/rt/mt ? -55 o c to +105 o c temperature range ? operational environment: - intrinsic total-dose: 100 krad(si) - sel immune < 110 mev-cm 2 /mg ? packaging options: - 484-pin ceramic land grid, column grid and ball grid array packages ? standard microcircuit drawing 5962-13238 - qml q, q+, and v ? applications - nuclear power plant controls - critical transportation systems - high-altitude avionics - medical electronics - x-ray cargo scanning - spaceborne computer - system controller boards - avionics processing boards introduction the UT700 features a seven stage pipelined monolithic, high- performance, fault-tolerant sparc tm v8/leon 3ft processor. l1 cache consists of 16kb for both instruction and data caches. a reed solomon ed ac provides fault-tolerant protection for sdram. integer performance is 1.2 dmips / mhz. rmap protocol is suppor ted for all four spacewire ports. the UT700 provides a 32-bit master/target pci interface, including a 16 bit user i/o inte rface for off-chip peripherals. a compliant 2.0 amba bus interface integrates the on-chip leon 3ft, spacewire, ethernet, memo ry controller, cpci, can bus, mil-std-1553, spi and programma ble interrupt peripherals. the UT700 is sparc v8 compliant; therefore, developers may use industry standard compilers, kernels, and development tools. a full software development suite is available including a c/c++ cross-compiler system based on gcc and the newlib embedded c-library. bcc includes a small run-time kernel with interrupt support and pthreads library. for multi-t hreaded applications, a sparc tm compliant port of the ecos r eal-time kernel, rtems 4.10, and vxworks 6.x is supported. standard products UT700 32-bit fault-tolerant sparc tm v8/leon 3ft processor datasheet march 2015 www.aeroflex.com/leon
2 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 1.0 introduction the UT700 leon 3ft processor is based upon the industry-standard sparc v8 architecture. the system-on-chip incorporates the sparc v8 core and the peripheral blocks indicated below. th e core and peripherals communi cate internally via the amba (advanced microcontroller bus arch itecture) interconnect. th is bus is comprised of the ahb (advanced high-speed bus) which is used for high-speed data transfer, and the apb (advanced peri pheral bus) which is used for low-speed data transfer. figure 1. UT700 functional block diagram the leon 3ft architectur e includes the following peripheral blocks: ? leon3 sparc v8 integer uni t with 16kb instruction cach e and 16kb of data cache ? ieee-754 floating point unit ? debug support unit ? uart, jtag, spacewire, pci, and ethernet debug links ? 8/16/32-bit memory controller with bch edac for external prom and sram ? 32-bit sdram controller with reed solomon edac for external sdram ? timer unit with three 32-bit timers and watchdog ? interrupt controller for 15 in terrupts in two priority levels ? 16-bit general purpose i/o port (gpio) which can be used as external interrupt sources ? up to four spacewire links with rmap on all channels ? mil-std-1553 interf ace supports bc/rt/mt ? up to two can controllers ? ethernet with support for mii ? cpci interface with 8-channel arbiter debug support unit jtag debug link leon 3ft ieee-754 fpu mul/div mmu 4x4kb data cache 4x4kb instr cache ahb interface spw w/ rmap (4) pci bridge ethernet mac can (2) spi mil- std- 1553 ahb controller ahb/apb bridge ft memory controller apb uart timers (4) int ctrl gpio clock gating 512mb prom 256mb i/o up to 1gb sram up to 1gb sdram amba ahb amba apb
3 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.0 pin identification and description pin function description i cmos input is cmos input schmitt o cmos output i/o cmos bi-direct od cmos open drain pci-i pci input pci-o pci output pci-i/o pci bi-direct pci-3 pci three-state 2.1. system signals notes: 1. this pin is actively driven low and must be tied to v dd through a pull-up resistor. 2.2 address bus pin name function pin number reset value description 484 clga sysclk i y20 -- main system clock nodiv i e19 -- clock divider input. set to ?1? for 1x memory clock, ?0? for 1/2x memory clock, relative to sysclk. reset is l19 -- system reset error 1 od k19 -- processor error mode indi cator. this is an active low output. wdog 1 od j19 -- watchdog indicator. this is an active low output. pin name direction pin number reset value description 484 clga addr[0] o w5 low bit 0 of the address bus addr[1] o y5 low bit 1 of the address bus addr[2] o w6 low bit 2 of the address bus addr[3] o aa5 low bit 3 of the address bus addr[4] o y6 low bit 4 of the address bus addr[5] o ab5 low bit 5 of the address bus addr[6] o w7 low bit 6 of the address bus
4 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.3 data bus addr[7] o aa6 low bit 7 of the address bus addr[8] o y7 low bit 8 of the address bus addr[9] o aa7 low bit 9 of the address bus addr[10] o ab6 low bit 10 of the address bus addr[11] o w8 low bit 11 of the address bus addr[12] o ab7 low bit 12 of the address bus addr[13] o y8 low bit 13 of the address bus addr[14] o aa8 low bit 14 of the address bus addr[15] o w9 low bit 15 of the address bus addr[16] o ab8 low bit 16 of the address bus addr[17] o y9 low bit 17 of the address bus addr[18] o w10 low bit 18 of the address bus addr[19] o ab9 low bit 19 of the address bus addr[20] o y10 low bit 20 of the address bus addr[21] o aa9 low bit 21 of the address bus addr[22] o w11 low bit 22 of the address bus addr[23] o aa10 low bit 23 of the address bus addr[24] o y11 low bit 24 of the address bus addr[25] o ab10 low bit 25 of the address bus addr[26] o ab11 low bit 26 of the address bus addr[27] o aa11 low bit 27 of the address bus pin name direction pin number reset value description 484 clga data[0] i/o w12 high-z bit 0 of the data bus data[1] i/o w13 high-z bit 1 of the data bus data[2] i/o y12 high-z bit 2 of the data bus pin name direction pin number reset value description 484 clga
5 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel data[3] i/o aa13 high-z bit 3 of the data bus data[4] i/o aa12 high-z bit 4 of the data bus data[5] i/o ab13 high-z bit 5 of the data bus data[6] i/o w14 high-z bit 6 of the data bus data[7] i/o aa14 high-z bit 7 of the data bus data[8] i/o y13 high-z bit 8 of the data bus data[9] i/o w15 high-z bit 9 of the data bus data[10] i/o ab15 high-z bit 10 of the data bus data[11] i/o y14 high-z bit 11 of the data bus data[12] i/o ab14 high-z bit 12 of the data bus data[13] i/o w16 high-z bit 13 of the data bus data[14] i/o aa18 high-z bit 14 of the data bus data[15] i/o y15 high-z bit 15 of the data bus data[16] i/o ab16 high-z bit 16 of the data bus data[17] i/o aa15 high-z bit 17 of the data bus data[18] i/o ab17 high-z bit 18 of the data bus data[19] i/o aa16 high-z bit 19 of the data bus data[20] i/o aa19 high-z bit 20 of the data bus data[21] i/o w17 high-z bit 21 of the data bus data[22] i/o ab18 high-z bit 22 of the data bus data[23] i/o y16 high-z bit 23 of the data bus data[24] i/o y17 high-z bit 24 of the data bus data[25] i/o aa17 high-z bit 25 of the data bus data[26] i/o w18 high-z bit 26 of the data bus data[27] i/o ab19 high-z bit 27 of the data bus data[28] i/o y19 high-z bit 28 of the data bus data[29] i/o ab20 high-z bit 29 of the data bus data[30] i/o y18 high-z bit 30 of the data bus data[31] i/o aa20 high-z bit 31 of the data bus pin name direction pin number reset value description 484 clga
6 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.4 check bits 2.5 memory control signals pin name direction pin number reset value description 484 clga cb[0] i/o v19 high-z bit 0 of edac bch/rs checkbits cb[1] i/o aa21 high-z bit 1 of edac bch/rs checkbits cb[2] i/o y21 high-z bit 2 of edac bch/rs checkbits cb[3] i/o w19 high-z bit 3 of edac bch/rs checkbits cb[4] i/o y22 high-z bit 4 of edac bch/rs checkbits cb[5] i/o w20 high-z bit 5 of edac bch/rs checkbits cb[6] i/o w22 high-z bit 6 of edac bch/rs checkbits cb[7] i/o w21 high-z bit 7 of edac bch/rs checkbits cb[8] i/o v18 high bit 8 of edac rs checkbits cb[9] i/o u18 high bit 9 of edac rs checkbits cb[10] i/o t18 high bit 10 of edac rs checkbits cb[11] i/o r18 high bit 11 of edac rs checkbits cb[12] i/o p18 high bit 12 of edac rs checkbits cb[13] i/o n18 high bit 13 of edac rs checkbits cb[14] i/o m18 high bit 14 of edac rs checkbits cb[15] i/o m19 high bit 15 of edac rs checkbits pin name direction pin number reset value description 484 clga write o v21 high prom and i/o write enable strobe oe o u19 high prom and i/o output enable ios o t20 high i/o area chip select roms[0] o v22 high prom chip select roms[1] o u20 high prom chip select rwe[0] o u22 high sram write enable strobe rwe[1] o t19 high sram write enable strobe
7 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.6 sdram rwe[2] o t22 high sram write enable strobe rwe[3] o t21 high sram write enable strobe ramoe[0] o v20 high sram output enable ramoe[1] o r21 high sram output enable ramoe[2] o r20 high sram output enable ramoe[3] o r22 high sram output enable ramoe[4] o r19 high sram output enable rams[0] o p22 high sram chip select rams[1] o p20 high sram chip select rams[2] o p21 high sram chip select rams[3] o p19 high sram chip select rams[4] o n19 high sram chip select read o k20 high sram, prom, and i/o read indicator bexc i k22 -- bus exception brdy i k21 -- bus ready pin name direction pin number reset value description 484 clga sdclk o ab12 high sdram clock sdras o n22 high sdram row address strobe sdcas o n20 high sdram column address strobe sdwe o n21 high sdram write enable sdcs[0] o m21 high sdram chip select sdcs[1] o m22 high sdram chip select sddqm[0] o l21 high sdram data mask sddqm[1] o m20 high sdram data mask sddqm[2] o l20 high sdram data mask pin name direction pin number reset value description 484 clga
8 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.7 can 2.0 interface 2.8 debug support unit (dsu) 2.9 jtag interface sddqm[3] o l22 high sdram data mask pin name direction pin number reset value description 484 clga can_rxd[0] i j20 -- can receive data can_txd[0] o j22 high can transmit data can_rxd[1] i j21 -- can receive data can_txd[1] o h22 high can transmit data pin name direction pin number reset value description 484 clga dsuact o h19 low dsumode indicator dsubre i h20 -- dsu break dsuen i g19 -- dsu enable dsurx i g20 -- dsu uart receive data dsutx o g21 high dsu uart transmit data pin name direction pin number reset value description 484 clga trst i f20 -- jtag reset tms i f21 -- jtag test mode select tck i g22 -- jtag clock tdi i f22 -- jtag test data input pin name direction pin number reset value description 484 clga
9 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.10 ethernet interface tdo o f19 undef jtag test data output pin name direction pin number reset value description 484 clga emdc o e22 low ethernet media interface clock erx_clk i d22 -- ethernet rx clock emdio i/o d20 high-z ethernet media interface data erx_col i e21 -- ethernet collision error erx_crs i e20 -- ethernet carrier sense detect erx_dv i d21 -- ethernet receiver data valid erx_er i c21 -- ethernet reception error erxd[0] i c22 -- ethernet receive data erxd[1] i b21 -- ethernet receive data erxd[2] i c20 -- ethernet receive data erxd[3] i b20 -- ethernet receive data etxd[0] o c19 low ethernet transmit data etxd[1] o c18 high ethernet transmit data etxd[2] o b18 low ethernet transmit data etxd[3] o b19 high ethernet transmit data etx_clk i a19 -- ethernet tx clock etx_en o a18 low ethern et transmit enable etx_er o a20 low ethernet transmit error. always driven low. edcldis i e17 -- ethernet edcl disable emdint i e18 -- ethernet management interface data interrupt pin name direction pin number reset value description 484 clga
10 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.11 general purpose i/o 2.12 spacewire interface pin name direction pin number reset value description 484 clga gpio[0] i/o b17 high-z bit 0 of general purpose i/o gpio[1] i/o c17 high-z bit 1 of general purpose i/o gpio[2] i/o a17 high-z bit 2 of general purpose i/o gpio[3] i/o d17 high-z bit 3 of general purpose i/o gpio[4] i/o c16 high-z bit 4 of general purpose i/o gpio[5] i/o d16 high-z bit 5 of general purpose i/o gpio[6] i/o c15 high-z bit 6 of general purpose i/o gpio[7] i/o d15 high-z bit 7 of general purpose i/o gpio[8] i/o c7 high-z bit 8 of general purpose i/o gpio[9] i/o b5 high-z bit 9 of general purpose i/o gpio[10] i/o d7 high-z bit 10 of general purpose i/o gpio[11] i/o a5 high-z bit 11 of general purpose i/o gpio[12] i/o d6 high-z bit 12 of general purpose i/o gpio[13] i/o c5 high-z bit 13 of general purpose i/o gpio[14] i/o c6 high-z bit 14 of general purpose i/o gpio[15] i/o d5 high-z bit 15 of general purpose i/o pin name direction pin number reset value description 484 clga spw_clk i a11 -- spacewire clock spw_rxs[0] i a16 -- spacewire receive strobe spw_rxd[0] i a15 -- spacewire receive data spw_txs[0] o b16 low spacewire transmit strobe spw_txd[0] o b15 low spacewire transmit data spw_rxs[1] i a14 -- spacewire receive strobe spw_rxd[1] i a13 -- spacewire receive data
11 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.13 uart interface 2.14 pci address and data bus spw_txs[1] o b14 low spacew ire transmit strobe spw_txd[1] o b13 low spacewire transmit data spw_rxs[2] i a9 -- spacewire receive strobe spw_rxd[2] i a8 -- spacewire receive data spw_txs[2] o b9 low spacewire transmit strobe spw_txd[2] o b8 low spacewire transmit data spw_rxs[3] i a7 -- spacewire receive strobe spw_rxd[3] i a6 -- spacewire receive data spw_txs[3] o b7 low spacewire transmit strobe spw_txd[3] o b6 low spacewire transmit data pin name direction pin number reset value description 484 clga rxd i c12 -- uart receive data txd o c11 high uart transmit data pin name direction pin number reset value description 484 clga pci_ad[0] pci-i/o aa2 high-z bit 0 of pci address and data bus pci_ad[1] pci-i/o aa3 high-z bit 1 of pci address and data bus pci_ad[2] pci-i/o y1 high-z bit 2 of pci address and data bus pci_ad[3] pci-i/o y2 high-z bit 3 of pci address and data bus pci_ad[4] pci-i/o y3 high-z bit 4 of pci address and data bus pci_ad[5] pci-i/o w1 high-z bit 5 of pci address and data bus pci_ad[6] pci-i/o w2 high-z bit 6 of pci address and data bus pin name direction pin number reset value description 484 clga
12 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel pci_ad[7] pci-i/o w3 high-z bit 7 of pci address and data bus pci_ad[8] pci-i/o v2 high-z bit 8 of pci address and data bus pci_ad[9] pci-i/o v3 high-z bit 9 of pci address and data bus pci_ad[10] pci-i/o u1 high-z bit 10 of pci address and data bus pci_ad[11] pci-i/o u2 high-z bit 11 of pci address and data bus pci_ad[12] pci-i/o u3 high-z bit 12 of pci address and data bus pci_ad[13] pci-i/o t1 high-z bit 13 of pci address and data bus pci_ad[14] pci-i/o r2 high-z bit 14 of pci address and data bus pci_ad[15] pci-i/o r1 high-z bit 15 of pci address and data bus pci_ad[16] pci-i/o j1 high-z bit 16 of pci address and data bus pci_ad[17] pci-i/o k2 high-z bit 17 of pci address and data bus pci_ad[18] pci-i/o k1 high-z bit 18 of pci address and data bus pci_ad[19] pci-i/o g1 high-z bit 19 of pci address and data bus pci_ad[20] pci-i/o h3 high-z bit 20 of pci address and data bus pci_ad[21] pci-i/o h2 high-z bit 21 of pci address and data bus pci_ad[22] pci-i/o f1 high-z bit 22 of pci address and data bus pci_ad[23] pci-i/o f2 high-z bit 23 of pci address and data bus pci_ad[24] pci-i/o e1 high-z bit 24 of pci address and data bus pci_ad[25] pci-i/o e2 high-z bit 25 of pci address and data bus pci_ad[26] pci-i/o f3 high-z bit 26 of pci address and data bus pci_ad[27] pci-i/o d1 high-z bit 27 of pci address and data bus pci_ad[28] pci-i/o d2 high-z bit 28 of pci address and data bus pci_ad[29] pci-i/o e3 high-z bit 29 of pci address and data bus pci_ad[30] pci-i/o d3 high-z bit 30 of pci address and data bus pci_ad[31] pci-i/o c1 high-z bit 31 of pci address and data bus pin name direction pin number reset value description 484 clga
13 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.15 pci control signals notes: 1. this pin must be tied to v dd through a pull-up resistor as spec ified in the pci local bus specification revision 2.1 section 4.3.3. 2.16 pci arbiter pin name direction pin number reset value description 484 clga pci_rst pci-i c3 -- pci reset input pci_clk pci-i c2 -- pci clock input pci_c/be [0] pci-i/o v1 high-z pci bus command and byte enable pci_c/be [1] pci-i/o p2 high-z pci bus command and byte enable pci_c/be [2] pci-i/o h1 high-z pci bus command and byte enable pci_c/be [3] pci-i/o g2 high-z pci bus command and byte enable pci_par pci-i/o p1 high-z pci parity checkbit pci_frame 1 pci-3 l1 high-z pci cycle frame indicator pci_irdy 1 pci-3 l2 high-z pci initiator ready indicator pci_trdy 1 pci-3 m1 high-z pci target ready indicator pci_stop 1 pci-3 n1 high-z pci target stop request pci_devsel 1 pci-3 m2 high-z pci device select pci_perr 1 pci-3 n2 high-z pci parity error indicator pci_idsel pci-i g3 -- pci initialization device select pci_req pci-o a4 high-z pci request to arbiter in point to point configuration pci_gnt pci-i b2 -- pci bus access indicator in point to point configura- tion pci_host pci-i ab3 -- pci host enable input (connect to sysen in pci bus) pin name direction pin number reset value description 484 clga pci_arb_req[0] pci-i b4 -- pci arbiter bus request pci_arb_req[1] pci-i ab4 -- pci arbiter bus request
14 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.17 serial periph eral interface (spi) 2.18 mil-std-1553 signals pci_arb_req[2] pci-i y4 -- pci arbiter bus request pci_arb_req[3] pci-i t3 -- pci arbiter bus request pci_arb_req[4] pci-i p3 -- pci arbiter bus request pci_arb_req[5] pci-i m3 -- pci arbiter bus request pci_arb_req[6] pci-i k3 -- pci arbiter bus request pci_arb_req[7] pci-i c4 -- pci arbiter bus request pci_arb_gnt[0] pci-o b3 high-z pci arbiter bus grant pci_arb_gnt[1] pci-o aa4 high-z pci arbiter bus grant pci_arb_gnt[2] pci-o w4 high-z pci arbiter bus grant pci_arb_gnt[3] pci-o r3 high-z pci arbiter bus grant pci_arb_gnt[4] pci-o n3 high-z pci arbiter bus grant pci_arb_gnt[5] pci-o l3 high-z pci arbiter bus grant pci_arb_gnt[6] pci-o j3 high-z pci arbiter bus grant pci_arb_gnt[7] pci-o a3 high-z pci arbiter bus grant pin name direction pin number reset value description 484 clga spiclk o e12 spi clock spimosi o e13 spi master out slave in spimiso i e11 -- spi master in slave out spislvsel o e10 spi select pin name direction pin number reset value description 484 clga 1553clk i b11 -- mil-std-1553b clock pin name direction pin number reset value description 484 clga
15 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.19 power and ground pins 1553rxa i c13 -- mil-std-1553b receive positive a 1553rxa i d12 -- mil-std-1553b receive negative a 1553rxb i c8 -- mil-std-1553b receive positive b 1553rxb i c9 -- mil-std-1553b receive negative b 1553rxena o d11 high-z mil-std-1553b receive enable a 1553rxenb o d9 high-z mil-std-1553b receive enable b 1553txinha o d13 high-z mil-std-1553b transmit inhibit a 1553txinhb o d10 high-z mil-std-1553b transmit inhibit b 1553txa o d14 high-z mil-std-1553b transmit positive a 1553txa o c14 high-z mil-std-1553b transmit negative a 1553txb o b10 high-z mil-std-1553b transmit positive b 1553txb o c10 high-z mil-std-1553b transmit negative b pin name pin number description 484 clga v dd b1, b12, b22, e7, e9, e14, e16, f6, f10, f13, f17, g5, g9, g14, h6, h8, h10, h13, h15, j7, j16, k5, k8, k15, k17, l6, m6, n5, n8, n15, n17, p7, p16, r6, r8, r10, r13, r15, t5, t9, t14, u6, u9, u11, u12, u14, u17, v10, v13, aa1, aa22 i/o supply voltage v ss a1, a12, a22, e6, f4, g4, g8, g11, g12, g15, g17, h4, h7, h16, h18, j2, j4, j9, j14, k4, k10, k13, l7, l11, l12, l17, m7, m11, m12, m17, n4, n10, n13, p4, p9 , p14, r4, r7, r16, t2, t4, t8, t15, t17, u4, u10, u13, v4, v5, v8, v11, v12, v15, ab1, ab22 i/o supply ground v ddc a2, a21, e5, f8, f15, g7, g10, g13, g16, g18, h5, h9, h11, h12, h14, h17, j6, j8, j15, k7, k16, l8, l15, l18, m4, m8, m15, n7, n16, p6, p8, p15, r5, r9, r11, r12, r14, r17, t7, t10, t13, t16, u8, u15, v6, v17, ab2, ab21 core supply voltage v ssc a10, e8, e15, f5, f7, f9, f11, f12, f14, f16, f18, g6, h21, j5, j10, j11, j12, j13, j17, k6, k9, k11, k12, k14, k18, l5, l9, l10, l13, l14, l16, m5, m9, m10, m13, m14, m16, n6, n9, n11, n12, n14, p5, p10, p11, p12, p13, p17, t6, t11, t12, u5, u7, u16, u21, v7, v14, v16 core supply ground pin name direction pin number reset value description 484 clga
16 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 2.20 bootstrap signals the states of the following signals are latched in upon the rising edge of reset in order to configure the UT700 for the indica ted operation. n/c d4, d18, e4, j18, l4, v9 no connect. these pins may be left floating, or tied to v dd or v ss unused d8 this pin may be left floating or tied to v ss unused d19 this pin must be tied to v ss pin name function gpio[1:0] sets the data width of the prom area 00: 8 bits 01: 16 bits 10: 32 bits 11: not used gpio[2] enable edac checking of the prom area 0: edac disabled 1: edac enabled gpio[7:4] set the spw clock divisor link bits in the spw clock divisor register gpio[15:12] sets the least significant address nibble of the ip and mac address for the ethernet debug commu- nication link (edcl) pin name pin number description 484 clga
17 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.0 ac and dc electrical specifications 3.1 absolute maximum ratings 1 notes: 1. stresses greater than those listed in the following table can result in permanent damage to the device. these parameters can not be violated. 2. per mil-std-883, method 1012, section 3.4.1, pd = (t j (max)-t c (max))/ jc symbol description min max units v ddc core supply voltage -0.3 1.85 v v dd i/o supply voltage -0.3 5.2 v v in input voltage any pin v ss - 0.3 v dd + 0.3 v p d 2 maximum power dissipation permitted @ t c = 105 o c -- 4 w t j junction temperature -- 150 o c jc thermal resistance, junction to case 484 clga/ccga/cbga -- 5 o c/w t stg storage temperature -65 150 o c esd hbm esd protection (human body model) class 2 2000 -- v
18 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.2 recommended op erating conditions (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55c to 105c) 3.3 operational environment the UT700 processor includes the following seu mitigation features: * cache memory error-detecting of up to 4 errors per tag or 32-bit word * autonomous and software transparent error handling * no timing impact due to error detection or correction notes: 1. tid irradation per mil-std-883, test me thod 1019, condition a. post irradiation electrical testin g performed at room temper ature. 2. worst case temperature of t c = +105 o c, v dd = 3.6v, v dd = 1.3v. 3. contact factory for additional inform ation regarding the determ ination of the inherent and multiple-bit upset rates. 4. the error rate calculation was performed using spacerad 6.0 fo r a geosynchronous orbit in th e adams 90% worst-case environme nt with 100mil al shielding. symbol description min max units v ddc core supply voltage 1.1 1.3 v v dd i/o supply voltage 3.0 3.6 v v in input voltage any pin 0 v dd v t c case operating temperature -55 105 o c t r rise time, all cmos and pci inputs (0.1v dd to 0.9v dd ) -- 20 ns t f fall time, all cmos and pci inputs (0.9v dd to 0.1v dd ) -- 20 ns parameter limit units total ionizing dose (tid) 1 1e5 rad (si) single event latchup immune (sel) 2 < 110 mev-cm 2 /mg single event upset (seu) 3, 4 inherent register upset rate 5.2e-7 errors/device-day single event upset (seu) 3, 4 multiple-bit error (mbe) rate which over- comes internal error detection & correction architecture 2.8e-11 mbe/device-day
19 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.4 power supply operating charact eristics (pre- and post-radiation) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) symbol description conditions min max units i ddcs standby core power sup- ply quiescent current v ddc = 1.3v, v dd = 3.6v all clock inputs at 0mhz t c = -55 o c and 25 o c -- 8 ma t c = 105 o c -- 100 rha: r t c = 25 o c -- 50 i dds standby i/o power sup- ply quiescent current v ddc = 1.3v, v dd = 3.6v all clock inputs at 0mhz t c = -55 o c and 25 o c -- 0.7 ma t c = 105 o c -- 2
20 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.5 dc characteristics for lvcmos3 inputs (pre- and post-radiation) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. jtag inputs are not tested. 2. capacitance is measured for initial qu alification and when design changes might affect the input/output capacitance. symbol description conditions min max units v ih 1 high-level input voltage 0.7v dd -- v v il 1 low-level input voltage -- 0.3v dd v v t+ positive going threshold voltage for schmitt inputs -- 0.7v dd v v t- negative going threshold voltage for schmitt inputs 0.3v dd -- v v h hysteresis voltage for schmitt inputs 0.4 -- v i in input leakage current (all inputs except pull-ups and pull-downs) v in = v dd -- 1 a v in = v ss -1 -- i in input leakage current fo r pins with internal pull-up resistors (cb[15:8], emdint , and nodiv) v in = v dd -10 10 a v in = v ss -100 -10 i in input leakage current fo r pins with internal pull-down resistors (edcldis, spimiso, 1553clk, 1553rxa, 1553rxa , 1553rxb, and 1553rxb ) v in = v dd +10 +150 a v in = v ss -10 10 c in 2 input pin capacitance f = 1mhz; v dd = 0v, v ddc = 0v -- 16 pf
21 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.6 dc characteristics for lvcmos3 outputs (pre- and post-radiation) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. jtag outputs are not tested. 2. except open-drain output. 3. guaranteed by design. 4. capacitance is measured for initial qu alification and when design changes might affect the input/output capacitance. symbol description conditions min max units v ol1 1 low-level output voltage (all outputs except those listed below and in section 3.8) i ol = 100 a--0.25v i ol = 4ma -- 0.4 v oh1 1,2 high-level output voltage (all outputs except those listed below and in section 3.8) i oh = -100 av dd -0.25 -- v i oh = -4ma 2.4 -- v ol2 low-level output voltage (gpio[15:0], spw_txd[3:0], spw_txs[3:0], txd) i ol = 100 a--0.25v i ol = 12ma -- 0.4 v oh2 high-level output voltage (gpio[15:0], spw_txd[3:0], spw_txs[3:0], txd) i oh = -100 av dd -0.25 -- v i oh = -12ma 2.4 -- v ol3 low-level output voltage (write , oe , ios , roms[1:0] , rwe [3:0] , ramoe [4:0] , rams[4:0] , sdcs[1:0] , sdras , sdcas , sdwe , sdclk, read, sddqm[3:0], addr[27:0], data[31:0] and cb[15:0]) i ol = 100 a--0.25v i ol = 24ma -- 0.4 v oh3 high-level output voltage (write , oe , ios , roms[1:0] , rwe [3:0] , ramoe [4:0] , rams[4:0] , sdcs[1:0] , sdras , sdcas , sdwe , sdclk, read, sddqm[3:0], addr[27:0], data[31:0] and cb[15:0]) i oh = -100 av dd -0.25 -- v i oh = -24ma 2.4 -- v ol4 low-level output voltage (spiclk, spimosi, spislvsel) i ol = 100 a--0.25v i ol = 8ma -- 0.4 v oh4 high-level output voltage (spiclk, spimosi, spislvsel) i oh = -100 av dd -0.25 -- v i oh = -8ma 2.4 -- i oz three-state output current v o = v dd -10 10 a v o = v ss -10 10 i os 3 short-circuit output current (all outputs except pci outputs) v o = v dd ; v dd = 3.6v -- 130 ma v o = v ss ; v dd = 3.6v -65 -- c out 4 output pin capacitance f = 1mhz; v dd = 0v, v ddc = 0v -- 16 pf
22 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.7 ac electrical characteristic s for lvcmos3 inputs and outputs (pre- and post-radiation) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. reference figure 17 for test load. figure 2. system clock and sdclk timing diagram symbol description conditions min max units f clk system clock frequency -- 166 mhz t high system clock high time 2.4 -- ns t low system clock low time 2.4 -- ns t dsd 1 system clock to sdram clock propagation delay 2.0 6.0 ns t dsd t dsd t dsd t dsd 1/f t t low t 1/f clk t high sysclk sdclk sdclk (sysclk / 2)
23 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.8 dc electrical characteristics for pc i inputs (pre- an d post-radiation) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. capacitance is meas ured for initial qualification and when design ch anges might affect the input/output capacitance. 3.9 dc electrical characteristics for pc i outputs (pre- and post-radiation) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. guaranteed by design. 2. capacitance is meas ured for initial qualification and when design ch anges might affect the input/output capacitance. symbol description conditions min max units v ih high-level input voltage 0.5v dd -- v v il low-level input voltage -- 0.3v dd v i in input leakage current v in = v dd -- +10 a v in = v ss -10 -- c in 1 input pin capacitance f = 1mhz; v dd = 0v, v ddc = 0v -- 22 pf symbol description conditions min max units v oh high-level output voltage (pci_ad[31:0], pci_c/be [3:0], pci_rst , pci_idsel, pci_frame , pci_irdy , pci_trdy , pci_devsel , pci_stop , pci_perr , pci_par) i oh = -500 a0.9v dd -- v v ol low-level output voltage (pci_ad[31:0], pci_c/be [3:0], pci_rst , pci_idsel, pci_frame , pci_irdy , pci_trdy , pci_devsel , pci_stop , pci_perr , pci_par) i ol = 1500 a--0.1v dd v i oz three-state output current v o = v dd -10 +10 a v o = v ss -10 +10 i os 1 short-circuit output current v o = v dd ; v dd = 3.6v -- 270 ma v o = v ss ; v dd = 3.6v -130 -- c out 2 output pin capacitance f = 1mhz; v dd = 0v, v ddc = 0v -- 22 pf
24 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 3.10 ac electrical charac teristics for pci inputs (pre- and post-radiation) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) figure 3. pci clock timing diagram symbol description conditions min max units f pci_clk pci clock frequency -- 33 mhz t high pci clock high time 11 -- ns t low pci clock low time 11 -- ns 1/f pci_clk t low t t high 1/f t pci_clk
25 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.0 timing specifications 4.1 power sequencing and reset (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. guaranteed by design. symbol description conditions min max units t vcd 1 v dd valid to v ddc delay v dd > 3.0v; v ddc > 1.1v 0 -- ns t vhbz 1 v dd valid to control signals high-z (write , oe , ios , roms[1:0] , rwe[3:0] , ramoe [4:0] , read sdwe , and sdcs[1:0]) v dd valid to outputs high-z ([data[31:0], cb[15:0] , and gpio[15:0]) v dd > 1.5v; v ddc = 0v -- 4 t clk t chbv 1 v ddc valid to control signals valid-inactive (write , oe , ios , roms[1:0] , rwe[3:0] , ramoe [4:0] , read sdwe , and sdcs[1:0] ) v dd > 3.0v; v ddc > 1.1v -- 4 t clk t reset1 1 v ddc valid to reset deassert v ddc > 1.1v 4 -- t clk t reset2 1 reset deasserted to outputs valid-active (roms[0] and oe ) -- 12 t clk t reset3 1 reset asserted to control signals valid- inactive (write , oe , ios , roms[1:0] , rwe[3:0] , ramoe [4:0] , read sdwe , and sdcs[1:0]) reset asserted to outputs high-z (data[31:0], cb[15:0], and gpio[15:0]) -- 4 t clk
26 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel figure 4. power sequencing and reset timing diagram 4.1.1. power sequencing for optimal power sequencing, both power-up and power-down, ramp both v dd and v ddc together. during power-up, if v ddc > v dd + 0.3v, excessive current or dama ge may occur to the device. during power down, it is acceptable for v dd to be less than v ddc by more than 0.3v as long as v ddc is not actively driven. 4.1.2 bus control and bi-direct fail-safe circuitry in order to prevent bus contention on the external memory interface while v ddc is ramping up, the UT700 has functionality to ensure that the bi-direct an d memory bus control signals described in section 4.1 will be in a high-z state t vhbz delay after v dd reaches 1.5v. the core logic will put these signals into their valid-inactive states t chbv clock cycles after v ddc reaches 1.1v. aeroflex recommends that users place pull-up resistors on the indicated output enable, write enable, and chip select pins, and a pull- down resistor on the read pin, if t vcd is greater than 100ns. this will prevent bus capacitance or transien ts from inadvertently placing these pins in an activ e state, which could result in external memory devices driving the address and data buses. 4.1.3 reset circuitry the reset circuitry is controlled by the core logic; therefore, the circuitry is functional only after v ddc reaches its minimum operat- ing voltage of 1.1v. after v ddc is stable, the system must continue to assert reset for a minimum of t reset1 clock cycles before it can be de-asserted. asserting reset for less time could result in the reset signal not being recognized. the UT700 will begin fetching code from external memory no more than t reset2 clock cycles after reset is de-asserted. control signals roms[0] and oe will be driven to their valid-act ive states in order for the UT700 to begin fetching code from prom. during normal operation, the indicated bus control signals will go to a valid-inactive state, and the bi-directs will go to a h igh-z state, within t reset3 clock cycles after the assertion of reset . valid-inactive valid-active valid-inactive valid-active t reset3 t vhbz t reset3 t reset2 t chbv t vhbz t reset1 t vcd sysclk v dd 3.3v v ddc 1.2v reset memory bus tri-state outputs 0v 0v control signals
27 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel
28 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel boot strap programming on gpio data on pins gpio[2:0], gapio[7:4] and gpio[15:12] are latched on the rising edge of reset. the states of gpio[2:0] determine the data width of the prom area, and enable edac for the prom area. chapter 3 of the user?s manual describes the value of these inputs to achieve the required operatio n. the states of gpio[7:4] provides a means to configure the spacewire clock divis or link bits in the clock divisor register. the states of gpio[15:12 ] set the least significant addre ss nibble of the ip and mac a ddress for the ethernet debug co mmunication link (edcl). in order for the state of gpio pins to be properly latched, aeroflex recommends placing pull-up or pull-down resistors on these pins to ensure that the setup and hold timing is met. the states of these pins should be statically set prior to the rising edge of reset .
29 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.2 output timing characterist ics for memory interface, error , and wdog (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. all outputs are measured using the load conditions shown in figure 17. 2. cb[7] is not tested in the case of bch edac. 3. high-z defined as +/-300mv change from steady state. 4. guaranteed by design. symbol description min max units t1a 1 sdclk to addr[27:0] valid 1.5 8.5 ns t1b 1 sdclk to sdcs[1:0] valid 2 7.5 ns t1c 1 sdclk to output valid sdras , sdcas , and sdwe 1.5 8.5 ns t1d 1 sdclk to sddqm[3:0] valid 2.5 8.5 ns t1e 1 sdclk to output valid (write , oe , ios , roms[1:0] , rwe [3:0] , ramoe [4:0] , rams[4:0] , and read) 18ns t2 1,2 sdclk to output valid (data[31:0] and cb[15:0]) 2.5 8.5 ns t3 1,2,3 sdclk to output high-z (data[31:0] and cb[15:0]) 2.5 8.5 ns t4 1 sdclk to signal low (error and wdog 4 ) -- 10 ns t8 1,2,3 write or rwe[3:0] to output high-z (data [31:0] and cb[15:0]) 0.5 -- ns t9 1 skew from first memory output signal transition to last memory output signal transition -- 2 ns
30 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel figure 5. memory interface, error , and wdog output timing diagram t1e t4 t8 t3 t2 t1d t1c t1b t1a t9 sdclk addr[27:0] sdcs sdras , sdcas , and sdwe sddqm[3:0] write and rwe[3:0] data[31:0] and cb[15:0] error and wdog all other outputs
31 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.3 input timing characteri stics for memory interface (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. cb[7] is not tested in the case of bch edac. 2. supplied as a design limit. neither guaranteed nor tested. figure 6. memory interface input timing diagram symbol description min max units t5a 1 setup time to sdclk (data[31:0] and cb[15:0]) 1--ns t5b setup time to sdclk (bexc, and synchronous brdy ) 2--ns t6a 1 hold time from sdclk (data[31:0] and cb[15:0]) 1.5 -- ns t6b hold time from sdclk (synchronous brdy ) 0--ns t7 2 asynchronous brdy pulse width 1.5 -- t clk t6b t5b t6a t5a t7 sdclk data[31:0] and cb[15:0] bexc and synchronous brdy asynchronous brdy
32 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.4 timing characteristics for gen eral purpose input / output (gpio) (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. all outputs are measured using the load conditions shown in figure 17. figure 7. general purpose i/o timing diagram symbol description min max units t10 1 sdclk to gpio output valid (gpio[15:0]) -- 10 ns t10 sdclk gpio[15:0]
33 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.5 timing characterist ics spacewire interface (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. the spw_clk frequency must be less than or equal to 10x the sysclk frequency. for example, if spw_clk is running at 200mhz, the sysclk frequency must be greater than or equal to 20mhz. 2. functionally tested. 3. applies to both high pulse and low pulse. 4. a unit interval (ui) is defined as the nominal, or ideal, bit width. 5. guaranteed by design. 6. the spw_clk period must be less than or e qual to the minimum receive data/strobe bit width. figure 8. spacewire transmit timing diagram figure 9. spacewire receive timing diagram symbol description min max units t11 1,2 spw_clk period 5 -- ns t14 3,4,5 transmit data and strobe bit width variation (spw_txd[3:0] and spw_txs[3:0]) ui-600 ui+600 ps t15 5,6 receive data and strobe bit width (spw_rxd[3:0] and spw_rxs[3:0]) 5-- ns t16 5 receive data and strobe edge separation (spw_rxd[3:0] and spw_rxs[3:0]) 1/2*t11 + 0.5 -- ns t14 t14 t11 spw_clk spw_txd spw_txs t15 t16 t16 t15 spw_rxd spw_rxs
34 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.6 timing characteristics for pci interface (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. all outputs are measured using the load conditions shown in figure 17. 2. high-z defined as +/-300mv change from steady state. 3. pci_trdy , pci_stop , and pci_devsel timing is guaranteed by design when used as inputs. 4. pci_perr and pci_gnt are guaranteed by design. 5. guaranteed by design. symbol description min max units t17 1 pci_clk to output valid (pci_ad[31:0], pci_c/be [3:0], pci_par, pci_frame , pci_irdy , pci_tdry , pci_stop , pci_devsel , pci_perr , pci_req , and pci_arb_gnt[7:0] ) 213ns t18 1,2 pci_clk to output valid from high-z (pci_ad[31:0], pci_c/be [3:0], pci_par, pci_frame , pci_irdy , pci_tdry , pci_stop , pci_devsel , and pci_perr 213ns t19 1,2 pci_clk to output high-z (pci_ad[31:0], pci_c/be [3:0], pci_par, pci_frame , pci_irdy , pci_tdry , pci_stop , pci_devsel , and pci_perr -- 14 ns t20 3,4 setup time to pci_clk (pci_ad[31:0], pci_c/be [3:0], pci_par, pci_frame , pci_irdy , pci_tdry , pci_stop , pci_devsel , pci_perr , pci_idsel, pci_gnt , and pci_ar- b_req[7:0] ) 4--ns t21 3,4 hold time from pci_clk (pci_ad[31:0], pci_c/be [3:0], pci_par, pci_frame , pci_irdy , pci_tdry , pci_stop , pci_devsel , pci_perr , pci_idsel, pci_gnt , and pci_ar- b_req[7:0] ) 1--ns t22 5 pci_clk to reset deassertion 10 -- pci clocks t23a 5 pci_clk to pci_rst deassertion 10 -- pci clocks t23b 5 pci_rst assertion to pci_clk idle 10 pci clocks t24 pci_rst active to output high-z -- 40 ns
35 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel figure 10. pci timing diagram figure 11. timing relationships of clock and reset for pci core utilization figure 12. timing relationships of clock and reset for unused pci core t21 t20 t19 t18 t17 pci_clk all outputs bi-direct and all inputs tri-state outputs t24 t22 t23b t23a sysclk pci_clk pci_rst reset bi-direct and tri-state outputs t22 sysclk pci_clk reset pci_rst
36 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.7 timing characteristic s for ethernet interface (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. all outputs are measured using the load conditions shown in figure 17. 2. erx_er timing is gu aranteed by design. 3. erx_col and erx_crs are asynch ronous inputs and are not tested. 4. t amba is defined as t sysclk for nodiv = 1 and t sysclk * 2 for nodiv = 0. 5. guaranteed by design. figure 13. ethernet tran smit and receive timing figure 14. ethernet mdio interface timing symbol description conditions min max units t25 1 etx_clk to output valid (etxd[3:0], and etx_en) -- 12 ns t26 2,3 setup time to erx_clk (erx_dv, erx_er, and erxd[3:0]) 1--ns t27 2,3 hold time from erx_clk (erx_dv, erx_er, and erxd[3:0]) 1--ns t28 1 emdc to output valid (emdio) -4+t amba 4 4+t amba 4 ns t29 5 setup time to emdc (emdio) 10 -- ns t30 5 hold time from emdc (emdio) 10 -- ns t27 t26 t25 etx_clk all outputs erx_clk all inputs t30 t29 t28 emdc emdio (output) emdio (input)
37 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.7 timing characteristics for mil-std-1553 interface 2 (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. all outputs are measured using the load conditions shown in figure 17. 2. the 1553rxa, 1553rxa , 1553rxb and 1553rxb inputs are resynchronized internally. figure 15. mil-std-1553 interface timing symbol description conditions min max units t31 1 1553clk to output valid (1553rxena, 1553rxenb, 1553tx- inha, 1553txinhb, 1553txa, 1553txa , 1553txb, and 1553txb ) -- 20 ns t31 1553clk all outputs
38 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.7 timing characteristics for spi 2 (v dd = 3.3v + 0.3v; v ddc = 1.2v + 0.1v; t c = -55 o c to 105 o c) notes: 1. all outputs are measured using the load conditions shown in figure 17. 2. the spimiso input is resynchronized internally. figure 16. serial periph eral interface (spi) timing symbol description conditions min max units t32 1 spiclk to output valid (spimosi) -2 2 ns t32 t32 spiclk spimosi
39 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 4.8 test conditions for timing specifications figure 17. equivalent load circuit for timing characteristics tests c l = 50 pf for ate test load c l =15 pf for benchtop test load v dd v dd 100 100 c l
40 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 5.0 packaging figure 18. 484-lead ceramic land grid array
41 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel figure 19. 484-lead cera mic column grid array
42 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel figure 20. 484-lead ceramic ball grid array
43 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel 7.0 ordering information UT700 leon 3ft package option associated lead finish (z) 484-clga (c) gold (s) 484-ccga (a) hot solder dipped (c) 484-cbga (a) hot solder dipped lead finish: (note 1) (c) = gold (a) = hot solder dipped or tinned screening level: (note 2 & 3) (p) = prototype (temperature range: 25 o c only) (e) = hirel (temperature range: -55 o c to +105 o c) case outline: (z) = 484-ceramic land grid array (s) = 484-ceramic column grid array (c) = 484-ceramic ball grid array UT700 32-bit leon 3ft UT700 - * * * notes: 1. lead finish (a or c) must be specified. 2. prototype flow per aeroflex manufacturin g flows document. devices are tested at 25 o c only. radiation is neither tested nor guaranteed. 3. hirel flow per aeroflex manufacturing flows docu ment. radiation is neither tested nor guaranteed.
44 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel UT700 leon 3ft: smd lead finish: (note 1) (c) = gold (f) = solder case outline: (x) = 484-ceramic land grid array package (y) = 484-ceramic column grid array screening level: (q) = qml class q device type: (note 2) (01) = UT700 (temperature range: -55 o c to +105 o c) (02) = UT700 assembled to aeroflex?s q+ flow (temp range: -55 o c to +105 o c) drawing number: 13238 total dose: (r) = 1e5 rad(si) federal stock class number: no options 5962 * 13238 ** * * * notes: 1. lead finish is ?c? (gold) only. 2.aeroflex?s q+ assembly flow, as defined in section 4.2.2.d of the smd, provides qml-q product through the smd that is manufac tured with aerof- lex?s standard qml-v flow, and has comple ted qml-v qualification per mil-prf-38535.
45 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services described herein at any time without notice. consult aeroflex or an authorized sales representa tive to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, ex cept as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service fro m aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. this product is controlled for export under the export admini stration regulations (ear). a license from the u.s. government is required prior to the export of th is product from th e united states. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel
46 36-00-00-000 ver. 1.3.1 aeroflex microelectroni cs solutions - hirel data sheet revision history revision & date description of change 11/19/13 ver. 1.0.0 release of preliminary data sheet 8/26/14 ver. 1.1.0 release production datasheet page 1: corrected sel immune page 17: corrected vddc, vdd limits, and note 3 temperature page 18: moved operational environment table from section 5 to 3.3 and updated page 19: added iddcs, idds limits from tbd page 20: added iin and iin limits (to bo und the range for pull up/down resistors) page 22: corrected tdsd limits page 23: corrected iin and ioz limits page 32: corrected symbols t14, t15, t1 6, and the correspond ing timing diagrams page 39: moved the operational environment table to section 3.3 on page 18 pages 40-42: corrected package drawings 11/21/14 1.2.0 page 2: changed figure 1 data and in str cache values from 2x4kb to 4x4kb page 16: added gpio[2] entry to bootstrap signals table. page 28:re-wrote section 4.1.4 page 43:corrected smd lead finish designator. page all: added footer march 2015 ver. 1.3.1 page 17: removed note 3 and changed the maximum junc tion temperature value from 125c to 150c in the absolute maximum ratings table. page 26: rewrote section 4.1.1 on power sequencing.

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